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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_pdm_pcm_config_v2_t Struct Reference<div class="ingroups"><a class="el" href="group__group__pdm__pcm__v2.html">PDM_PCM_v2   (PDM-PCM Converter v2)</a> &raquo; <a class="el" href="group__group__pdm__pcm__data__structures__v2.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>PDM-PCM initialization configuration. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:abe656e99f149e5ee9f843e74b26110ea"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#abe656e99f149e5ee9f843e74b26110ea">clkDiv</a></td></tr>
<tr class="memdesc:abe656e99f149e5ee9f843e74b26110ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">PDM Clock Divider This configures a frequency of PDM CLK.  <a href="#abe656e99f149e5ee9f843e74b26110ea">More...</a><br /></td></tr>
<tr class="separator:abe656e99f149e5ee9f843e74b26110ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74899000f0aef947bb7206197e29b2f1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__pdm__pcm__enums__v2.html#ga24b6a433876052cf822c1a4007a00cf9">cy_en_pdm_pcm_clock_sel_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#a74899000f0aef947bb7206197e29b2f1">clksel</a></td></tr>
<tr class="memdesc:a74899000f0aef947bb7206197e29b2f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface clock clk_if selection.  <a href="#a74899000f0aef947bb7206197e29b2f1">More...</a><br /></td></tr>
<tr class="separator:a74899000f0aef947bb7206197e29b2f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae583eb4efb8c80d6c57e9c502894501b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__group__pdm__pcm__enums__v2.html#ga6772333ee7eab35a0f8b1d9db5239302">cy_en_pdm_pcm_halve_rate_sel_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#ae583eb4efb8c80d6c57e9c502894501b">halverate</a></td></tr>
<tr class="memdesc:ae583eb4efb8c80d6c57e9c502894501b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Halve rate sampling.  <a href="#ae583eb4efb8c80d6c57e9c502894501b">More...</a><br /></td></tr>
<tr class="separator:ae583eb4efb8c80d6c57e9c502894501b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ca07c66529d253e44650a1a4a1b156f"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#a4ca07c66529d253e44650a1a4a1b156f">route</a></td></tr>
<tr class="memdesc:a4ca07c66529d253e44650a1a4a1b156f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver.  <a href="#a4ca07c66529d253e44650a1a4a1b156f">More...</a><br /></td></tr>
<tr class="separator:a4ca07c66529d253e44650a1a4a1b156f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac93d868c2f7d56889c72b859cd302a6e"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#ac93d868c2f7d56889c72b859cd302a6e">fir0_coeff_user_value</a></td></tr>
<tr class="memdesc:ac93d868c2f7d56889c72b859cd302a6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIR 0 filter coefficient enable.  <a href="#ac93d868c2f7d56889c72b859cd302a6e">More...</a><br /></td></tr>
<tr class="separator:ac93d868c2f7d56889c72b859cd302a6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad563e0d9af280a46d6040da1ba3d23e2"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#ad563e0d9af280a46d6040da1ba3d23e2">fir1_coeff_user_value</a></td></tr>
<tr class="memdesc:ad563e0d9af280a46d6040da1ba3d23e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIR 1 filter coefficient enable.  <a href="#ad563e0d9af280a46d6040da1ba3d23e2">More...</a><br /></td></tr>
<tr class="separator:ad563e0d9af280a46d6040da1ba3d23e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b04538e631d31018d9b4bf80135ddfe"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structcy__stc__pdm__pcm__fir__coeff__t.html">cy_stc_pdm_pcm_fir_coeff_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#a6b04538e631d31018d9b4bf80135ddfe">fir0_coeff</a> [8]</td></tr>
<tr class="memdesc:a6b04538e631d31018d9b4bf80135ddfe"><td class="mdescLeft">&#160;</td><td class="mdescRight">The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7.  <a href="#a6b04538e631d31018d9b4bf80135ddfe">More...</a><br /></td></tr>
<tr class="separator:a6b04538e631d31018d9b4bf80135ddfe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2ff5fad3ed25286e20277c5bf25a91b1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="structcy__stc__pdm__pcm__fir__coeff__t.html">cy_stc_pdm_pcm_fir_coeff_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__pdm__pcm__config__v2__t.html#a2ff5fad3ed25286e20277c5bf25a91b1">fir1_coeff</a> [14]</td></tr>
<tr class="memdesc:a2ff5fad3ed25286e20277c5bf25a91b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">The (symmetric) 55-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR1_COEFF0, ..., FIR1_COEFF13.  <a href="#a2ff5fad3ed25286e20277c5bf25a91b1">More...</a><br /></td></tr>
<tr class="separator:a2ff5fad3ed25286e20277c5bf25a91b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="abe656e99f149e5ee9f843e74b26110ea"></a>
<h2 class="memtitle"><span class="permalink"><a href="#abe656e99f149e5ee9f843e74b26110ea">&#9670;&nbsp;</a></span>clkDiv</h2>

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<p>PDM Clock Divider This configures a frequency of PDM CLK. </p>
<p>The configured frequency is used to operate PDM core. The value that user assigns here will be incremented by 1 and assigned internally. For example, if the clkDiv value is 0, it is internally incremented by 1. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a74899000f0aef947bb7206197e29b2f1">&#9670;&nbsp;</a></span>clksel</h2>

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<p>Interface clock clk_if selection. </p>
<p><a class="el" href="group__group__pdm__pcm__enums__v2.html#ga24b6a433876052cf822c1a4007a00cf9">cy_en_pdm_pcm_clock_sel_t</a> </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ae583eb4efb8c80d6c57e9c502894501b">&#9670;&nbsp;</a></span>halverate</h2>

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<p>Halve rate sampling. </p>
<p><a class="el" href="group__group__pdm__pcm__enums__v2.html#ga6772333ee7eab35a0f8b1d9db5239302">cy_en_pdm_pcm_halve_rate_sel_t</a> </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a4ca07c66529d253e44650a1a4a1b156f">&#9670;&nbsp;</a></span>route</h2>

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<p>Specifies what IOSS data input signal "pdm_data[]" is routed to a specific PDM receiver. </p>
<p>Each PDM receiver j has a dedicated 1-bit control field: PDM receiver j uses DATA_SEL[j]. The 1-bit field DATA_SEL[j] specification is as follows: '0': PDM receiver j uses data input signal "pdm_data[j]". '1': PDM receiver j uses data input signal "pdm_data[j ^ 1]" (the lower bit of the index is inverted) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ac93d868c2f7d56889c72b859cd302a6e">&#9670;&nbsp;</a></span>fir0_coeff_user_value</h2>

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<p>FIR 0 filter coefficient enable. </p>
<p>User has to configure the coeff values. 0: Disabled. 1: Enabled </p>

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<p>FIR 1 filter coefficient enable. </p>
<p>User has to configure the coeff values. 0: Disabled. 1: Enabled </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a6b04538e631d31018d9b4bf80135ddfe">&#9670;&nbsp;</a></span>fir0_coeff</h2>

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<p>The (symmetric) 30-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR0_COEFF0, ..., FIR0_COEFF7. </p>
<p>The FIR filter coefficients have no default values: the coefficients MUST be programmed BEFORE the filter is enabled. By Default FIR0 is disabled and is only used for 8Khz and 16 Khz sample frequencies </p>

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<p>The (symmetric) 55-taps finite impulse response (FIR) filter with 14-bit signed coefficients (in the range [-8192, 8191]) are specified by FIR1_COEFF0, ..., FIR1_COEFF13. </p>
<p>The (default) FIR filter has built in droop correction. The filter gain (sum of the coefficients) is 13921 and the default coefficients (as specified by FIR1_COEFFx.DATA0/1[13:0]) are: (-2, 21), (26, -17), (-41, 25), (68, -33), (-107, 41), (160, -48), (-230, 54), (325, -56), (-453, 51), (631, -31), (-894, -21), (1326, 172), (-2191, -770), (4859, 8191) </p>

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